SOTERIA: Exploiting Process Variation to Enhance Hardware Security Using Photonic NoC Architectures

At a Glance

SOTERIA is a novel security enhancement framework using a two-part solution for improving hardware security for Photonic Network-on-Chip (PNoC) architectures, significantly reducing the chance of a hardware trojan snooping on private data. The first part is a circuit-level scheme that uses encryption and authentication signatures to help prevent snooping data. The second part is an architecture-level scheme that uses a reservation waveguide and a switching methodology to further prevent snooping data. The combination of these two schemes significantly reduces the possibility of snooping attacks in PNoC architectures.


The complexity of hardware in modern chip-multiprocessors has increased to cope with the growing performance demands of modern Big Data and cloud computing applications. Chip-multiprocessor devices may use photonic networks-on-chip (PNoCs) to form packet-switched network fabrics over the processing cores to transfer data either between on-chip components for inter-core communication or between devices for inter-chip communication. Recent developments in silicon photonics have enabled the integration of photonic components to interconnect with CMOS circuits on a chip. PNoCs provide several prolific advantages over traditional metallic counterparts, including the ability to communicate at near light speed, larger bandwidth density and lower dynamic power dissipation.


SOTERIA provides hardware-circuit-level encryption for inter-core communication of PNoC devices to protect data from snooping attacks. This includes encryption using authentication signatures that are based on process variations that inherently occur during the fabrication of the photonic communication device. The hardware level encryption can facilitate high bandwidth on-chip data transfers while preventing hardware-based trojans embedded in components of the PNoC device or preventing external snooping devices from snooping data. Additionally, there is an architecture-level reservation operation that decouples the photonic waveguide and a reservation waveguide to secure the photonic communication device from internal or external snooping or manipulation.


  • Technology provides circuit-level security enhancement as well as architecture-level security enhancement
  • Enhances hardware security with minimal overheads of up to 10.6% in average latency and up to 13.3% in energy-delay-product


  • Easily implementable in existing dense-wavelength-division-multiplexing based phontonic networks-on-chip without major changes in architecture
Last Updated: November 2023
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Sudeep Pasricha
Sai Vineel Reddy Chittamuru
Ishan G Thakkar